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| 1 ? fn8250.0 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2005. all rights reserved all other trademarks mentioned are the property of their respective owners. x45620 dual voltage monitor with integrated system battery sw itch and eeprom features ? dual voltage monitoring ? active low reset outputs ? two standard reset threshold voltages ?factory programmable threshold ? lowline output ? zero delayed por ? reset signal valid to v cc = 1v ? system battery switch-over circuitry ? selectable watchdog timer ?(0.15s, 0.4s, 0.8s, off) ? 256kbits of eeprom ? built-in inadvertent write protection ?power-up/power-down protection circuitry ?protect 0, 1/4, 1/2 or all of eeprom array with programmable block lock ? protection ?in circuit programmable rom mode ? minimize eeprom programming time ?64 byte page write mode ?self-timed write cycle ?5ms write cycle time (typical) ? 400khz 2-wire interface ? 2.7v to 5.5v power supply operation ? available package ? 20-lead tssop ? dual supervisor ? battery switch and output description the intersil x45620 combines power-on reset control, battery switch circuit, watchdog timer, supply voltage supervision, secondary volt age supervision, block lock protect and serial eeprom in one package. this combination lowers system cost, reduces board space requirements, and in creases reliability. applying power to the device activates the power-on reset circuit which holds reset active for a period of time. this allows the powe r supply and oscillator to stabilize before the processor can execute code. a system battery switch circuit compares v cc (v1mon) with v batt input and connects v out to whichever is higher. this provides voltage to external sram or other circuits in the event of ma in power failure. the x45620 can drive 50ma from v cc and 250a from v batt . the device switches to v batt when v cc drops below the low v cc voltage threshold and v batt > v cc . block diagram watchdog timer reset data register command decode, test & control logic sda scl v cc reset & watchdog timebase power-on, generation v cc monitor + - reset low voltage status register protect logic eeprom watchdog transition detector wp 512 x 512 address-decoder v trip1 logic v2 monitor + - v trip2 logic system switch reset /mr lowline v2fail v2mon v batt v out (v1mon) battery array device select logic s0 s1 batt-on wdo v out v out (32k x 8 bit) data sheet july 29, 2005
2 fn8250.0 july 29, 2005 description (continued) the watchdog timer provides an independent protec- tion mechanism for microcontrollers. when the micro- controller fails to restart a timer within a selectable time out interval, the device activates the wdo signal. the user selects the interval from three preset values. once selected, the interval does not change, even after cycling the power. the device?s low v cc detection circuitry protects the user?s system from low volt age conditions, resetting the system when v cc (v1mon) falls below the mini- mum v cc trip point (v trip1 ). reset is asserted until v cc returns to prop er operating level and stabilizes. a second voltage monitor circuit tracks the unregulated supply or monitors a second power supply voltage to provide a power fail warning. intersil?s unique circuits allow the threshold for either voltage monitor to be reprogrammed to meet special needs or to fine-tune the threshold for applications requiring higher preci- sion. (contact factory for custom v trip options) pin configuration ordering information 20-pin tssop s0 nc s1 1 2 3 4 nc v cc (v1mon) batt-on v out 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 nc lowline v2fail v2mon reset /mr wdo v ss v batt nc nc scl sda wp v cc range v trip1 range v trip2 range package operating temperature range part number 4.75?5.5v 4.5?4.75v 2.55?2.7v 20l tssop 0c?70c x45620v20 -40c?85c x45620v20i 2.7?5.5v 2.55?2.7v 1.7?1.80v 20l tssop 0c?70c x45620v20-2.7 -40c?85c x45620v20i-2.7 pin description pin name function 1 s 0 device select input. this pin has an internal pull down resistor. (>10m ? typical) 2 s 1 device select input. this pin has an internal pull down resistor. (>10m ? typical) 3 nc no internal connections 4lowline low v cc detect . this open drain output signal goes low when v cc < v trip1 and immediately goes high when v cc > v trip1 . 5 nc no internal connections 6v2fail v2 voltage fail output. this open drain output goes low when v2mon is less than v trip2 and goes high when v2mon exceeds v trip2 . there is no power-up reset delay circuitry on this pin. 7v2mon v2 voltage monitor input. when the v2mon input is less than the v trip2 voltage, v2fail goes low. this input can monitor an unregulated power s upply with an external resistor divider or can monitor a second power supply with no external components. connect v2mon to v ss or v cc when not used. x45620 3 fn8250.0 july 29, 2005 8 reset /mr reset output/manual reset input . this is an input/output pin. reset output . this is an active low, open drain output which goes active whenever v cc falls below the minimum v cc sense level. when reset is active communication to the device is interrupt- ed. reset remains active until v cc rises above the minimum v cc sense level for t purst . reset also goes active on power-up and remains active for t purst after the power supply stabilizes. mr input . this is an active low debounced input. when mr is active, the reset pins are assert- ed. when mr is releas ed, the reset remains asserted for t purst , and then released. 9wdo watchdog output. wdo is an active low, open drain output which goes active whenever the watchdog timer goes active. wdo remains active for 150ms, then returns to the inactive state. 10 v ss ground 11 sda serial data. sda is a bidirectional pin used to transfer data into and out of the device. it is an open drain output, requires the use of a pull-up resistor. 14 scl serial clock. the scl input is used to clock all data into and out of the device. 12?13 nc no internal connections 15 v batt battery supply voltage. this input provides a backup supply in the event of a failure of the pri- mary v cc voltage. the v batt voltage typically provides the supply voltage necessary to maintain the contents of sram and also powers the internal logic to ?stay awake.? if unused, connect v batt to ground. 16 v out output voltage. v out = v cc if v cc > v trip1 . if v cc < v trip1 , then, v out = v cc if v cc > v batt +0.03 v out = v batt if v cc < v batt -0.03 note: there is hysteresis around v batt 0.03v point to avoid oscillation at or near the switchover voltage. a capacitance of 0.1f must be connected to vout to ensure stability. 17 batt-on battery on. this cmos output goes high when the v out switches to v batt and goes low when v out switches to v cc . it is used to drive a external p-channel fet when v cc = v out and current requirements are greater than 50ma. the purpose of this output is to drive an exter nal fet to get higher operating currents when the v cc supply is fully functional. in the event of a v cc failure, the battery voltage is applied to the v out pin and the external transistor is turned off. in this ?backup condition,? the battery only needs to supply enough voltage and current to keep sram devices from losing their data-there is no communication at this time. 18 nc no connect 19 wp write protect. the wp pin works in conjunction with a nonvolatile wpen bit to ?lock? the setting of the watchdog timer control and the memory write protect bits. this pin has an internal pull down resistor. (>10m ? typical) 20 v cc (v1mon) supply voltage/v1 voltage monitor input. when the v1mon input is less than the vtrip1 voltage, reset and lowline go active. pin description (continued) pin name function x45620 4 fn8250.0 july 29, 2005 absolute maximum ratings temperature under bias ................... -65c to +135c storage temperature ......... ............... -65c to +150c voltage on any pin with respect to v ss ...................................... -1.0v to +6v d.c. output current (all output pins except v out )............................. 5ma d.c. output current v out .................................... 50ma lead temperature (soldering, 10 seconds)........ 300c comment stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only; functional operation of the device (at these or any ot her conditions above those listed in the operational sections of this specification) is not implied. exposure to absolute maximum rating con- ditions for extended periods ma y affect device reliability. recommended operating conditions temperature min max commercial 0c 70c industrial -40c +85c device option supply voltage -2.7 2.7v-5.5v blank 4.75v-5.5v d.c. operating characteristics (over recommended operating condit ions unless otherwise specified) symbol parameter limits unit test conditions min typ (6) max i cc1 v cc supply current (active) (excludes i out ) read memory array (excludes i out ) write nonvolatile memory 1.5 3.0 ma scl = 400khz v out , reset , lowline = open note 1 i cc2 v cc supply current (passive) (excludes i out ) 50 a sda = v cc , any input = v ss or v cc : v out , reset , lowline = open, note 2 i cc3 v cc current (battery backup mode) (excludes i out ) 1av batt = 2.8v, v out , re- set = open, note 4, 1 i batt1 v batt current (excludes i out )1av out = v cc , note 4 i batt2 v batt current (excludes i out ) (battery backup mode) 50 a v out = v batt , v batt =2.8v v out , reset = open, note 4 v out1 output voltage (v cc > v batt + 0.03v or v cc > v trip1 v cc ? 0.05 v cc ? 0.5 v cc ? 0.02 v cc ? 0.2 v v i out = -5ma i out = -50ma v out2 output voltage (v cc < v batt + 0.03v and v cc < v trip1 ) {battery backup} v batt ? 0.2 v i out = -250a v olb output (batt-on) low voltage 0.4 v i ol = 3.0ma (5v) i ol = 1.0ma (3v) v bsh battery switch hysteresis (v cc < v trip1 ) 30 -30 mv mv power-up power-down, note 4 v trip1 v cc reset trip point voltage 4.5 2.55 4.62 2.62 4.75 2.7 v x45620 x45620-2.7 v trip2 v2mon reset trip point voltage 2.55 1.7 2.62 1.75 2.7 1.8 v x45620 x45620-2.7 x45620 5 fn8250.0 july 29, 2005 notes: (1) the device enters the active state after any start, and rema ins active until 9 clock cycles later if the device select bits in the slave address byte are incorrect; 200ns after a stop ending a read operation; or t wc after a stop ending a write operation. (2) the device goes into standby: 200ns after any stop, except those that initiate a high voltage write cycle; t wc after a stop that initiates a high voltage cycle; or 9 clock cycles afte r any start that is not followed by the corre ct device select bits in the slave addre ss byte. (3) v il min. and v ih max. are for reference only and are not tested. (4) this parameter is guaranteed by characterization. capacitance t a = +25c, f = 1mhz, v cc = 5v equivalent a.c. load circuit at 5v v cc a.c. test conditions v olr output (reset , lowline , wdo , v2fail ) low voltage 0.4 v i ol = 3.0ma (5v) i ol = 1.0ma (3v) two wire interface v il input (sda, s0, s1, scl, wp) low voltage -0.5 v cc x 0.3 v note 3 v ih input (sda, s0, s1, scl, wp) high voltage v cc x 0.7 v cc + 0.5 v note 3 i li input leakage current (sda, s1, s0, scl, wp) 10 a v ols output (sda) low voltage 0.4 v i ol = 3.0ma (5v) i ol = 1.0ma (3v), note 4 d.c. operating characteristics (continued) (over recommended operating condit ions unless otherwise specified) symbol parameter limits unit test conditions min typ (6) max symbol test max unit conditions c out output capacitance (sda, reset , v2fail , lowline , batt-on, wdo )8pfv out = 0v, note 1, 4 c in input capacitance (sda, scl, s0, s1, wp) 6 pf v in = 0v, note 1, 4 v cc sda 30pf 1.53k ? v cc 1.53k ? 30pf batt-on reset 4481 ? v2fail lowline wdo input pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10ns input and output timing level v cc x 0.5 x45620 6 fn8250.0 july 29, 2005 a.c. characteristics (over recommended operating condit ions, unless otherwise specified) read & write cycle limits serial output timing power-up timing (5) notes: (5) t pur and t puw are the delays required from the time v cc is stable until the specified operation can be initiated. these parameters are not 100% tested. (6) typical values are for t a = 25c and nominal supply voltage (5v) (7) cb = total capacitance of one bus line in pf. bus timing symbol parameter min max unit test conditions f scl scl clock frequency 400 khz t in pulse width suppression time at inputs 50 ns note 4 t aa scl low to sda data out valid 0.1 0.9 s note 4 t buf time the bus must be free before a new transmission can start 1.3 s note 4 t low clock low period 1.3 s note 4 t high clock high period 0.6 s note 4 t su:sta start condition setup time 0.6 s t hd:sta start condition hold time 0.6 s t su:dat data in setup time 100 ns note 4 t hd:dat data in hold time 0 s note 4 t su:sto stop condition setup time 0.6 s note 4 t dh data output hold time 50 ns note 4 symbol parameter min max unit test conditions t r sda and scl rise time 20 + .1cb 300 ns note 4 t f sda and scl fall time 20 + .1cb 300 ns note 4 t su:s0, s1, wp s0, s1, and wp setup time 0.6 ns note 4 t hd:s0, s1, wp s0, s1, and wp hold time 0 ns note 4 cb capacitive load for each bus line 400 pf note 4, 7 symbol parameter max unit test conditions t pur power-up to read operation 1 ms note 4 t puw power-up to write operation 5 ms note 4 t su:sta t hd:sta t hd:dat t su:dat t low t su:sto t r t buf scl sda in sda out t dh t aa t f t high x45620 7 fn8250.0 july 29, 2005 s 0 , s 1 , and wp pin timing write cycle limits notes: (8) t wc is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. it is the maximum time the device requires to automatically complete the internal write operation. the write cycle time is the time from a valid stop condition of a write sequence to the end of the internal erase/write cycle. during the write cycle, the x45620 bus interface circuits are disabled, sd a is allowed to remain high, and the device does not respond to its slave address. write cycle timing t su: s0, s1, wp scl sda in s 0 , s 1 and wp slave address byte clk 1 clk 9 t hd: s0, s1, wp symbol parameter min typ (6) max unit test conditions t wc (8) write cycle time ? 5 10 ms note 4 scl sda 8 th bit word n ack t wc stop condition start condition x45620 8 fn8250.0 july 29, 2005 power-up and po wer-down timing v cc to lowline timings v2mon to v2fail timings t vb1 reset t vb2 t purst t purst t rpd v batt v cc v bat 0v v out v trip1 0v v out v cc batt-on v cc lowline v trip v batt v trip1 0v v oh v ol v trip1 0v t r t rpd t rpd t f v trip2 0v t r t rpd2 t rpd2 t f v2mon v2fail x45620 9 fn8250.0 july 29, 2005 reset output timing notes: (9) this measurement is from 10% to 90% of the supply voltage. wdt restart timing minimum wdt restart timing symbol parameter min typ (6) max unit test conditions t purst reset time out period pup = 0 pup = 1 75 400 150 600 250 800 ms note 4 t rpd v trip1 to reset (power-down only), v trip1 to lowline 10 20 s note 4 t rpd2 v trip2 to v2fail 10 20 s note 4 t lr lowline to reset delay (power-down only) 100 200 300 ns note 4 t f v cc /v2mon fall time 1000 s note 4, 9 t r v cc /v2mon rise time 1000 s note 4, 9 v rvalid reset valid v cc 1v t vb1 v batt + 0.03 v to batt-on (logical 0) 20 s note 4 t vb2 v batt ? 0.03 v to batt-on (logical 1) 20 s note 4 t hd:sta 11 fn8250.0 july 29, 2005 system battery switch as long as v cc exceeds the low voltage detect thresh- old v trip1 , v out is connected to v cc through a 5 ? (typical) switch. when the v cc has fallen below v trip , then v cc is applied to v out if v cc is equal to or greater than v batt + 0.03v. when v cc drops to less than v batt - 0.03v, then v out is connected to v batt through an 80 ? (typical) switch. v out typically sup- plies the system static ram voltage, so the switchover circuit operates to protect the contents of the static ram during a power failure. typically, when v cc has failed, the srams go into a lower power state and draw much less current than in their active mode. when v cc returns, v out switches back to v cc when v cc exceeds v batt +0.03v. there is a 60mv hystere- sis around this battery switch threshold to prevent oscillations between supplies. while v cc is connected to v out the batt-on pin is pulled low. the signal can drive external pass ele- ments to provide additional current to the external cir- cuits during normal operation. operation the device is in normal operation with v cc as long as v cc > v trip1 . it switches to the battery backup mode when v cc goes away. manual reset by connecting a push-button from mr to ground or driven by logic, the desi gner adds manual system reset capability. the reset pins is asserted when the push- button is closed and remain asserted for t purst after the push-button is released. this pin is debounced so a push-button connected directly to the device will have both clean falling and rising edges on mr . figure 2. example system connection condition mode of operation v cc > v trip1 normal operation. v cc > v trip1 & v batt = 0 normal operation without battery back up capability. 0 v cc < v trip1 and v cc < v batt battery backup mode; reset signal is asserted. no communica- tion to the device is allowed. v cc 5v reg + unregulated supply address decode enable sram addr v cc nmi reset 2-wire c v batt v2mon v ss batt-on v out v2fail reset sda, scl supercap dual p-channel fet v2mon provides early detection of power failure examples: irf 7756, fds9733a x45620 12 fn8250.0 july 29, 2005 two wire serial memory the memory portion of the device is a cmos serial eeprom array with intersil?s block lock protection. the array is internally organized as x 8. the device features two wire and software protocol allowing operation on a simple four-wire bus. two device select inputs (s 0 ?s 1 ) allow up to four devices to share a common two wire bus. a control register at the highest address location, ffffh, provides three write protection features: soft- ware write protect, block lock protect, and program- mable rom. the software write protect feature prevents any nonvolatile writ es to the device until the wel bit in the control register is set. the block lock protection feature gives the user eight array block pro- tect options, set by programming three bits in the con- trol register. the programmable rom feature allows the user to install the device with wp tied to v cc , write to and block lock the desired portions of the memory array in circuit, and then enable the in circuit program- mable rom mode by programming the wpen bit high in the control register. afte r this, the block locked por- tions of the array, including the control register itself, are protected from being erased if wp is high. intersil eeproms are designed and tested for appli- cations requiring extended endurance. inherent data retention is greater than 100 years. detailed pin descriptions serial clock (scl) the scl input is used to clock all data into and out of the device. serial data (sda) sda is a bidirectional pin used to transfer data into and out of the device. it is an open drain output and may be wire-ored with any number of open drain or open collector outputs. an open drain output requires the use of a pull-up resistor. for selecting typica l values, refer to the pull- up resistor selection graph at the end of this data sheet. device select (s 0 , s 1 ) the device select inputs (s 0 , s 1 ) are used to set bits in the slave address. this allo ws up to four devices to share a common bus. these inputs can be static or actively driven. if used static ally they must be tied to v ss or v cc as appropriate. if actively driven, they must be driven with cmos levels (driven to v cc or v ss ) and they must be constant between each start and stop issued on the sda bus. these pins have an active pull down internally and will be sensed as low if the pin is left unconnected. write protect (wp) wp must be constant between each start and stop issued on the sda bus and is always active (not gated). the wp pin has an active pull down to disable the write protection when the input is left floating. the write protect input controls the hardware write pro- tect feature. when held low, hardware write protec- tion is disabled. when this input is held high, and the wpen bit in the control register is set high, the control register is protected, preventing changes to the block lock protection and wpen bits. device operation the device supports a bidirectional bus oriented proto- col. the protocol defines any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. the device controlling the transfer is a master and the device being controlled is the slave. the master will always initia te data transf ers, and pro- vide the clock for both transmit and receive operations. therefore, the devic e will be considered a slave in all applications. clock and data conventions data states on the sda line can change only during scl low. sda state cha nges during scl high are reserved for indicating start and stop conditions. refer to figures 7 and 8. start condition all commands are preceded by the start condition, which is a high to low tr ansition of sd a when scl is high. the device continuous ly monitors the sda and scl lines for the start c ondition and will not respond to any command until this condition has been met. x45620 13 fn8250.0 july 29, 2005 figure 7. data validity figure 8. definition of start and stop stop condition all communications must be terminated by a stop con- dition, which is a low to high transition of sda when scl is high. the stop condition is also used to place the device into the standby power mode after a read sequence. a stop condition can only be issued after the transmitting device has released the bus. acknowledge acknowledge is a software convention used to indi- cate successful data transf er. the transmitting device, either master or slave, will release the bus after trans- mitting eight bits. during the ninth clock cycle the receiver will pull the sda line low to acknowledge that it received the eight bits of data. refer to figure 9. the device will respond with an acknowle dge after recognition of a start condition and its slave address. if both the device and a write operation have been selected, the device will re spond with an acknowledge after the receipt of each subsequent 8-bit word. in the read mode t he device will transmit eight bits of data, release the sda line and monitor the line for an acknowledge. if an acknowledge is detected and no stop condition is generate d by the master, the device will continue to transmit data . if an acknowledge is not detected, the device will term inate further data trans- missions. the master must t hen issue a stop condition to return the device to the standby power mode and place the device into a known state. figure 9. acknowledge response from receiver scl sda data stable data change scl sda start bit stop bit scl from data output from transmitter 1 89 data output fromreceiver start acknowledge master x45620 14 fn8250.0 july 29, 2005 device addressing following a start condition, th e master must output the address of the slave it is accessing. the first four bits of the slave address byte are the device type identi- fier bits. these must equal ?1010?. the next 3 bits are the device select bits ?0?, s 1 , and s 0 . this allows up to 4 devices to share a single bus. these bits are com- pared to the s 0 , s 1 , device select input pins. the last bit of the slave address byte defines the operation to be performed. when the r/w bit is a one, then a read operation is selected. when it is zero then a write operation is selected. refer to figure 10. after loading the slave address byte from the sda bus, the device compares the device type bits with the value ?1010? and the device select bits with the status of the device select input pins. if the compare is not successful, no acknowledge is output durin g the ninth clock cycle and the device returns to the standby mode. on power-up the internal address is undefined, so the first read or write operation must supply an address. the word address is either supplied by the master or obtained from an internal counter, depending on the operation. the master must supply the initial two word address bytes as shown in figure 10. the internal organization of the e 2 array is 512 pages by 64 bytes per page. the page address is partially contained in the word address byte 1 and partially in bits 7 through 6 of the word address byte 0. the byte address is contained in bits 5 through 0 of the word address byte 0. see figure 10. write operations byte write for a write operation, the device follows ?3 byte? proto- col, consisting of one slave address byte, one word address byte 1, and the word address byte 0, which gives the master access to any one of the words in the array. upon receipt of the word address byte 0, the device responds with an acknowledge, and waits for the first eight bits of data. after receiving the 8 bits of the data byte, the device again responds with an acknowledge. the master t hen terminates the transfer by generating a stop condition, at which time the device begins the internal write cycle to the nonvolatile memory. while the internal write cycle is in progress the device inputs are disabled and the device will not respond to any requests from the master. the sda pin is at high impedance. see figure 11. refer to bus tim- ing on page 21. figure 10. device addressing page write the device is capable of a 64 byte page write operation. it is initiated in the same manner as the byte write operation; but instead of terminating the write operation after the first data word is transferred, the master can transmit up to sixty-three more words. the device will respond with an acknowledge after the receipt of each word, and then the byte address is internally incre- mented by one. the page add ress remains constant. when the counter reaches the end of the page, it ?rolls over? and goes back to the first byte of the current page. this means that the master can write 64-bytes to the page beginning at any byte. if the master begins writing at byte 32, and load s 64-bytes, then the first 32-bytes are written to bytes 32 through 63, and the last 16 words are written to bytes 0 through 31. after- wards, the address counter would point to byte 32. if the master writes more than 64 bytes, then the previ- ously loaded data is overwritten by the new data, one byte at a time. 1 s 1 s 0 r/w device select 010 device type identifier slave address byte d7 d2 d1 d6 d5 d4 d3 data byte a2 a1 a0 a5 a4 a3 word address byte 0 * a10 a9 a8 a14 high order word address a11 x45620 word address byte 1 a13 a12 a7 a6 d0 *this bit is 0 for access to the array and 0 low order word address 1 for access to the control register x45620 15 fn8250.0 july 29, 2005 the master terminates the dat a byte loading by issuing a stop condition, which causes the device to begin the nonvolatile write cycle. as wi th the byte write operation, all inputs are disabled until completion of the internal write cycle. refer to figure 12 for the address, acknowledge, and data transfer sequence. stop and write modes stop conditions that terminate write operations must be sent by the master after sending at least 1 full data byte and it?s associated ack signal. if a stop is issued in the middle of a data byte, or before 1 full data byte + ack is sent, then the device will reset itself without performing the writ e. the contents of the array will not be affected. acknowledge polling the maximum write cycle ti me can be significantly reduced using acknowled ge polling. to initiate acknowledge polling, the mast er issues a start condi- tion followed by the slave address byte for a write or read operation. if the device is still busy with the inter- nal write cycle, then no ac k will be returned. if the device has completed the internal write operation, an ack will be returned and the host can then proceed with the read or write operation. refer to figure 13. figure 11. byte write sequence figure 12. page write sequence signals from the master sda bus signals from the slave s t a r t slave address s t o p a c k a c k a c k a c k byte 1 data 1 0 1 0 word address byte 0 s p 0 word address s 1 s 0 0 s t a r t s t o p a c k a c k a c k a c k a c k data (0) (n) 0 s p data 1 0 1 0 (0 n 64) signals from the master sda bus signals from the slave slave address byte 1 word address byte 0 word address s 1 s 0 0 x45620 16 fn8250.0 july 29, 2005 figure 13. acknowledge polling sequence read operations read operations are initiated in the same manner as write operations with the exception that the r/w bit of the slave address byte is set to one. there are three basic read operations: current address reads, ran- dom reads, and sequential reads. refer to bus tim- ing on page 21. current address read internally, the device contains an address counter that maintains the address of the last word read or written incremented by one. after a read operation from the last address in the array, the counter will ?roll over? to the first address in the array. after a write operation to the last address in a give n page, the counter will ?roll over? to the first address on the same page. upon receipt of the slave address byte with the r/w bit set to one, the device issues an acknowledge and then transmits the eight bits of the data byte. the master ter- minates the read operation when it does not respond with an acknowledge during the ninth clock and then issues a stop condition. refer to figure 14 for the address, acknowledge, and data transfer sequence. it should be noted that the ninth clock cycle of the read operation is not a ?don?t care.? to terminate a read operation, the master must either issue a stop condi- tion during the ninth cycle or hold sda high during the ninth clock cycle and th en issue a stop condition. note: after a power-up sequence, the first read cannot be a current address read. figure 14. current address read sequence random read random read operation allows the master to access any memory location in the ar ray. prior to issuing the slave address byte with the r/w bit set to one, the master must first perform a ?dummy? write operation. the master issues the star t condition and the slave address byte with the r/w bit low, receives an acknowledge, then issues the word address byte 1, receives another acknowledge, then issues the word address byte 0. after the device acknowledges receipt of the word address byte 0, the master issues another start condition and the slave address byte with the r/w bit set to one. this is followed by an acknowl- edge and then eight bits of data from the device. the master terminates the read operation by not respond- ing with an acknowledge and then issuing a stop con- dition. refer to figure 9 for the address, acknowledge, and data transfer sequence. the device will perform a similar operation called ?set current address? if a stop is issued instead of the sec- ond start shown in figure 15. the device will go into standby mode after the stop and all bus activity will be ignored until a start is detected. the effect of this oper- ation is that the new address is loaded into the address counter, but no data is output by the device. the next current address read operation will read from the newly loaded address. byte load completed by issuing stop. enter ack polling issue start issue slave address byte (read or write) ack returned? high cycle complete. continue sequence? continue normal read or write command sequence? proceed issue stop no yes yes issue stop no voltage the slave s t a r t slave address s t o p a c k data signals from the master sda bus signals from 1 sp 010 1 s 1 s 0 0 x45620 17 fn8250.0 july 29, 2005 figure 15. random read sequence figure 16. sequential read sequence sequential read sequential reads can be initiated as either a current address read or random read. the first data byte is transmitted as with the other modes; however, the master now responds with an acknowledge, indicating it requires additional data. the device continues to output data for each acknow ledge received. the master terminates the read operation by not responding with an acknowledge and then issu ing a stop condition. the data output is sequen tial, with the data from address n followed by the data from address n + 1. the address counter for read operations increments through all byte addresses, allowing the entire memory contents to be read during one operation. at the end of the address space the counter ?rolls over? to address 0000h and the device continues to output data for each acknowledge received. refer to figure 16 for the acknowledge and data transfer sequence. control register (cr) the control register is located in an area logically separated from the array and is only accessible via a byte write to the register address of ffffh. the con- trol register is physically part of the array. the cr can only be modified by performing a byte write operation directly to the address of the register and only one data byte is allowed for each register write operation. prior to initiating a nonvolatile write to the cr, the wel and rwel bits must be set using a two step process, with the whole sequence requiring 3 steps. the user must issue a stop, after sending this byte to the register, to initiate the high voltage cycle that writes pup, wd1, wd0, bp 1, bp0 and wpen to the nonvolatile bits. the part will not acknowledge any data bytes written after the first byte is entered. a stop must also be issued after a volatile register write oper- ation to put the device into standby. after a write to the cr, the address counter contents are undefined. the state of the cr can be read by performing a ran- dom read at the address of the register at any time. only one byte is read by the register read operation. the part will reset itself afte r the first byte is read. the master should supply a stop condition to be consistent with the bus protocol, but a stop is not required to end this operation. after the r ead of the cr, the address counter contents are reset to zero, but the user will be told these bits are undefined and instructed to do a random read. table 1. control register rwel: register write en able latch (volatile) the rwel bit must be set to ?1? prior to a write to control register. signals from the master sda bus signals from the slave s t a r t s t o p a c k a c k a c k 0 s t a r t 1 data a c k s p s 1010 slave address byte 1 word address byte 0 word address slave address s 1 s 0 0 s s t o p a c k a c k a c k a c k (1) (2) (n?1) (n) 1 (n is any integer greater than 1) p signals from the master sda bus signals from the slave slave address data data data data s 1 s 0 76543210 wpen wd1 wd0 bp1 bp0 rwel wel pup x45620 18 fn8250.0 july 29, 2005 wel: write enable latch (volatile) the wel bit controls the access to the memory and to the register during a write operation. this bit is a volatile latch that powers up in the low (disabled) state. while the wel bit is low, writes to any address, including any control registers will be ignored (no acknowledge will be issued after the data byte). t he wel bit is set by writing a ?1? to the wel bit and zeros to the other bits of the con- trol register. once set, wel remains set until either it is reset to 0 (by writing a ?0? to the wel bit and zeros to the other bits of the control register) or until the part powers up again. writes to wel bit do not cause a high voltage write cycle, so the device is ready for the next operation immediately after the stop condition. bp1, bp0: block protect bits (nonvolatile) the block protect bits, bp1 and bp0, determine which blocks of the array are write protected. a write to a pro- tected block of memory is ignored. the block protect bits will prevent write operations to one of four segments of the array. the partitions are described in table 2. wd1, wd0: watchdog timer bits (nonvolatile) the watchdog timer circuit monitors the micro- processor activity by monitoring the scl and sda pins. in normal operation, the microprocessor must periodically restart the watchdog timer to prevent wdo from going active. the watchdog timer is restarted on the first high to low transition on scl after a start command. the state of two nonvolatile control bits in the status register determines the watchdog timer period. the microprocessor can change these watchdog bits by writing to the status register. the watchdog timer oscillato r stops when in battery backup mode. it re-starts when v cc returns. write protect enable bit?wpen (nonvolatile) the write protect (wp) pin and the write protect enable (wpen) bit in the control register control the program- mable hardware write protect feature. hardware write protection is enabled when the wp pin is connected to v cc and the wpen bit is high, and disabled when wp pin is connected to ground. when the chip is in rom mode, nonvolatile writes are disabled to all non-volatile bits in the cr, including the block protect bits and the wpen bit itself, as well as to the block protected sections in the memory array. only the sections of the memory array that are not block protected can be written. note that since the wpen bit is write protected, it cannot be changed back to a low state; so write protection is enabled as long as the wp pin is held connected to v cc . pup: power-on reset (nonvolatile) the power-on reset time (t purst ) bit, pup, sets the initial power-on reset time. there are two standard settings. note 1. watchdog timer is shipped disabled. 2. the t purst time is set to 150ms at the factory. any changes to the contro l register take effect, following either the next command (read or write) or cycling the power to the device. the recommended procedure for changing the watchdog timer settings is to do a wren, followed by a write status register command. then execute a software loop to read the status register until an ack is returned (ack polling) co mplete the r ead operation. a valid alternative is to do a wren, followed by a write status register co mmand. then wait 10ms and do a read status command. table 2. block protect bits status register bit watchdog time out (typical) wd1 wd0 0 0 800 milliseconds 0 1 400 milliseconds 1 0 150 milliseconds 1 1 disabled (factory setting) pup time 0 150 ms (factory settings) 1 800 ms bp1 bp0 protected addresses array lock 0 0 none none (factory setting) 0 1 6000h - 7fffh (8k bytes) upper 1/4 (q4) 1 0 4000h - 7fffh (16k bytes) upper 1/2 (q3, q4) 1 1 0000h - 7fffh (32k bytes) full array (all) x45620 19 fn8250.0 july 29, 2005 table 3. write protect enable bit and wp pin function writing to the control register changing any of the nonvolatile bits of the control regis- ter requires the following steps: ? write a 02h to the cr to set the write enable latch (wel). this is a volatile operation, so there is no delay after the write. (operation preceeded by a start and ended with a stop). ? write a 06h to the cr to set both the register write enable latch (rwel) and the wel bit. this is also a volatile cycle. the zeros in the data byte are required. (operation preceeded by a start and ended with a stop). ? write a value to the cr that has all the control bits set to the desired state, with the wel bit set to ?1? and the rwel bit set to ?0?. this can be represented as nqrs t 01 u in binary, where n is the wpen bit and qrstu are the wd1, wd0, bp1, bp 0 and pup bits. (operation preceeded by a start and ended with a stop). since this is nonvolatile write cycle it will take up to 10ms to complete. the rwel bit is reset by this cycle and the sequence must be repeated to change the nonvolatile bits again. if bit 2 is set to ?1? in this third step ( nqrs t 11 u ) then the rwel bit remains set and the wpen, pup, wd1, wd0, bp1 and bp0 bits remain unchanged. ? a read operation occurring between any of the previ- ous operations will not inte rrupt the register write operation. ? the rwel bit cannot be rese t without writing to the nonvolatile control bits in the control register, power cycling the device or attempting a write to a write pro- tected block. ? changes made to the control register non-volatile bits become effective upon the next read operation of the control register. (power cycling will also activate changes to the control register). ? changes made to volatile bits in the register take effect immediately foll owing the last data bit. to illustrate, a sequence of wr ites to the device consist- ing of [02h, 06h, 02h] will reset all of the nonvolatile bits to 0 and clear the rwel bit. a sequence of [02h, 06h, 06h] will leave the nonvolatile bits unchanged and the rwel bit remains set. when resetting the wel bit, the operation goes active immediately following the last data bit. the device will, therefore, not respond with an ack after the reset wel command data byte. operational notes the device powers-up in the following state: ? the device is in the low power standby state. ? a ?start bit? is required to enter an active state to receive an instruction. ? the write enable latch (wel) is reset. ? the reset signal is active for t purst . data protection the following circuitry has been included to prevent inadverten t writes: ? the wel bit must be set before writing to the memory array. ? the wel and rwel bits must be set before writing to the nonvolatile bits of the control register. ? a valid slave byte and two address bytes must be sent to the device with a valid ack between each byte. ? a ?stop bit? must be receiv ed following a multiple of 8 data bits and completion of the data ack bit. ? during the time reset is active communication to the device are ignored. wp wpen memory array not block protected memory array block protected block lock bits wpen bit protection low x writes ok writes blocked writes ok writes ok software high 0 writes ok writes blocked writes ok writes ok software high 1 writes ok writes blocked writes blocked writes blocked hardware x45620 20 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn8250.0 july 29, 2005 packaging information note: all dimensions in inches (in parentheses in millimeters) 20-lead plastic, tsso p, package type v see detail ?a? .031 (.80) .041 (1.05) .169 (4.3) .177 (4.5) .252 (6.4) bsc .025 (.65) bsc .252 (6.4) .300 (7.62) .002 (.05) .006 (.15) .047 (1.20) .0075 (.19) .0118 (.30) 0 - 8 .010 (.25) .019 (.50) .029 (.75) gage plane seating plane detail a (20x) x45620 |
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